1. Field of the Invention
The present invention relates to a digital signal processing circuit adapted for use in a data demodulator of a magnetic disk recording/playback apparatus or the like.
2. Description of the Prior Art
FIG. 5 is a block diagram of a conventional data demodulator with a level tracking loop employed in a magnetic disk recording/playback apparatus as disclosed in U.S. patent application Ser. No. 07/963,905 (filed Oct. 20, 1992). The data demodulator comprises an A-D converter 11 for converting into a digital signal the output signal of an analog AGC amplifier which receives the output of a playback amplifier (denoted by reference numeral 44 in FIG. 4) and produces a signal of a fixed envelope level; an equalizer (FIR filter) 14 for equalizing the output signal of the A-D converter 11; a digital PLL circuit 16 for extracting a 0xc2x0 phase clock signal from the output Sk of the equalizer 14 and producing 0xc2x0 phase data which represents the phase Pk of a data existence point; a 0xc2x0 phase sample interpolator 15 supplied with the respective outputs of the equalizer 14 and the digital PLL circuit 16 and producing a signal amplitude level S0k at the data existence point (0xc2x0 phase); a level tracking loop 17 supplied with the signal amplitude level S0k from the interpolator 15 and producing a 0xc2x0 phase signal level average when the noise component included in the playback signal is averaged; and a Viterbi decoder 18 for producing detection data dk by executing maximum likelihood decode and decision of the data on the basis of both the signal amplitude level S0k outputted from the interpolator 15 and the 0xc2x0 phase signal level average outputted from the level tracking loop 17.
Since the output S0k of the interpolator 15 is delivered once per sampling interval Ts, merely one of two samples corresponds to a 0xc2x0 phase on the average. An effective signal Vk is supplied from the digital PLL circuit 16 to the Viterbi decoder 18 so as to serve as a signal which signifies whether the output S0k of the interpolator 15 has a 0xc2x0 phase amplitude level for decision of the data. The Viterbi decoder 18 is required to execute its operation of data decision merely when Vk=1.
The A-D converter 11 samples the analog playback signal from the AGC amplifier at a sampling frequency fs which is a predetermined multiple of the channel bit rate, and quantizes the sampled signal to have a predetermined signal word length. For example, the sampling frequency fs is set to a double of the channel bit rate.
The equalizer 14 eliminates the intercede interference derived from the band limit characteristics and so forth of the magnetic recording channel. A digital signal processing circuit can be realized by employing, e.g., a transversal type linear equalizer or the like.
The digital PLL circuit 16 synchronizes with the phase Pk of the data existence point on the basis of the signal sample Sk obtained by the use of a fixed-frequency clock signal. Since the detail of the digital PLL circuit 103 is disclosed in the aforementioned U.S. patent application Ser. No. 07/963,905, an explanation thereof is given here briefly with its schematic constitution shown in FIG. 6.
Referring to FIG. 6, an instantaneous phase calculator 50 receives, as an input, a sampled value Sk of the channel playback signal at a time t=kTs. On the basis of two successive signal samples obtained by using the fixed-frequency clock signal nonsynchronously with the input signal data, the instantaneous phase calculator 50 produces an instantaneous phase xcex94Pk as an output which represents the time from the existence time t=kTs of the signal sample Sk back to the signal waveform zero-crossing (candidate for 0xc2x0 phase) in the kth time slot. The unit of such output is the quantized phase number.
The instantaneous phase xcex94Pk is the distance from the 0xc2x0 phase having a phase value 0 to the time kTs and represents the value obtained on the basis of the time t=kTs. On the phase, 360xc2x0 corresponds to a digital value 2NPLL. The time Ts of one time slot width corresponds to 180xc2x0 on the phase, which is equal to a digital value 2NPLLxe2x88x921 with respect to the quantized phase number regarded as a unit. The instantaneous phase xcex94Pk is calculated on an assumption that the signal waveform between the successive two samples Sk and Skxe2x88x921 can be linearly approximated. The instantaneous phase xcex94Pk is added, as the phase data xcex94Pk is added, as the phase data xcex94Pk of NPLL bits, in an adder 51 to the phase Pkxe2x88x921 outputted from an internal phase register 56. The output of the adder 51 is multiplied by a modification coefficient xcex1 in a multiplier 53 and then is supplied to one input terminal of an AND gate 54.
Now an explanation will be given below with regard to a phase detector 52 for selecting the instantaneous phase data corresponding to the 0xc2x0 phase. The instantaneous phase xcex94Pk is calculated whenever the signal waveform has a zero-crossing. Therefore, depending on the channel coding notation, there may occur such a situation that the instantaneous phase is the one calculated at a point different from a 0xc2x0 phase where the data is essentially existent. In a partial response (hereinafter referred to as PRS) (1, 0, xe2x88x921) or the like, there may be a zero-crossing in an opposite phase as well as in a 0xc2x0 phase. It is accordingly necessary to select the calculated instantaneous phase output obtained only at the true 0xc2x0 phase. Therefore, in the case of a PRS (1, 0, 1) for example, temporary data is first detected by a ternary level predictor 524, and a phase control signal generator 528 generates a phase control signal modify_Pk relative to the instantaneous phase xcex94Pk decided to be a 0xc2x0 phase on the basis of such temporary data. And the phase control signal modify_Pk is supplied to the other input terminal of the AND gate 54. Consequently, only the detected instantaneous phase xcex94Pk (accurately, the output of the multiplier 53) alone is supplied via the AND gate 54 to the adder 55 and then is added to the output phase Pkxe2x88x921 of the register 56.
Both the 0xc2x0 phase data and the effective signal Vk are supplied to the 0xc2x0 sample interpolator 15 as the data that represents the position of the 0xc2x0 phase data existence point in the time slot.
A plurality of adders and multipliers are included in the feedback loop of the digital PLL circuit shown in FIG. 6, so that a total of the calculation delay time amounts to a great value (e.g., 30 to 40 nanoseconds). It is difficult in the feedback loop to execute a pipeline process, and the calculation in the loop needs to be completed within one sampling time. Therefore the calculation delay time is dominant to determine the minimum possible value of the sampling interval.
And an ACS (add-compare-store) loop included in the Viterbi decoder for updating the degree of likelihood limits the maximum value of the sampling interval similarly to the above.
Accordingly, even if the channel bit rate needs to be raised by increasing the linear density on the recording medium, there arises a problem that the rate is restricted by the speed of the circuit elements.
It is an object of the present invention to provide an improved digital signal processing circuit which is capable of raising the transmission rate of a playback channel despite an increase of the time required to execute a desired signal process such as demodulation.
According to one aspect of the present invention, there is provided a digital signal processing circuit which comprises a memory means for storing a digital signal obtained from a playback channel; a control means for writing the digital signal in the memory means at a first rate and reading out the digital signal from the memory means at a second rate lower than the first rate; and a processing means for executing a desired process relative to the digital signal read out from the memory means.
In such a digital signal processing circuit, the playback channel is a partial response channel associated with a disk.
The signal processing circuit further comprises an A-D converter for converting the analog signal obtained from the playback channel into a digital signal. The A-D converter is disposed in the preceding stage of the memory means and is driven in accordance with a first clock signal of a fixed frequency, and the processing means is driven in accordance with a second clock signal of another fixed frequency lower than that of the first clock signal. The control means generates a read/write control signal and a read/write address signal in response to the first fixed-frequency clock signal, the second fixed-frequency clock signal, a sector index signal and a data read command signal.
The processing means includes an equalizer for equalizing the digital signal, an interpolator for interpolating the 0xc2x0 phase data on the basis of the digital signal, and a decoder for decoding the digital signal with the maximum likelihood. Meanwhile the control means includes a first counter for counting the pulses of the first fixed-frequency clock signal to generate a write address signal; and a second counter for counting the pulses of the second fixed-frequency clock signal to generate a read address signal.
In the digital signal processing circuit of the constitution mentioned above, the digital signal is written in the memory means at a first rate by the control means and is read out therefrom at a second rate which is lower than the first rate. And then a desired process is executed relative to the digital signal thus read out from the memory means. Therefore the required signal processing rate may be lower than the transmission rate of the playback channel. Consequently, it becomes possible to raise the transmission rate of the playback channel despite the condition that the time required for the desired signal process such as demodulation is rendered longer.
Furthermore, due to the circuit constitution where the desired signal process for the digital signal written in the memory means at the first rate is read out therefrom at the lower second rate, the transmission rate of the playback channel can be raised in conformity with an increase of the disk recording density.